How to use the input's values in "always" definiton in Verilog

Question

I got the problem with using the input's value in Verilog. I write:

module reg_vector (INPUT, ICLK, IENBL, NR, OUT);
parameter k = 6;
parameter n = 3;
input [(8*k)-1:0] INPUT;
input ICLK;
input IENBL;
input [n-1:0] NR;

reg [n-1:0] temp;
output reg [7:0] OUT;

always@ (temp, posedge ICLK)
begin
    if (IENBL)
        begin
            OUT = INPUT[temp*8 : temp*8+8];
        end
end

endmodule

But got the error:

Error (10734): Verilog HDL error at reg_vector.v(25): temp is not a constant

How should I fix it? Thank you)

Answer 1

INPUT[temp*8 : temp*8+8] does not work because the : range syntax requires both sides to be a constant.
What you want is to use the +: array slicing: INPUT[temp*8 +: 8] The left hand side of +: allows variables and represents the starting index. The right hand side is the width and must be a constant. For more on +: see Indexing vectors and arrays with +:

Other issues:

1. Remove temp from the sensitivity list.
2. temp needs to be assigned to something
3. OUT should be assigned with non-blocking (<=) not blocking (=) since it is sequential logic.

always @(posedge ICLK) // no temp in sensitivity list
begin
  if (IENBL)
  begin
    OUT <= INPUT[temp*8 +: 8]; // non-blocking and +:
  end
end