$display vs $strobe vs $monitor in verilog?

What is the difference between $display vs $strobe vs $monitor in verilog? When in the event queue does each apply, and how do the statements interact? Can any statement inhibit another?

Solution

I'll be nice and summarize the LRM (Language Reference Manual), but you should read it. Everything is in IEEE Std 1800-2012 § 21.2 Display system tasks (Technically SystemVerilog, but these functions are identical.)

$display : print the immediate values
- § 21.2.1 The display and write tasks
$strobe : print the values at the end of the current timestep
- § 21.2.2 Strobed monitoring
$monitor : print the values at the end of the current timestep if any values changed. $monitor can only be called once; sequential call will override the previous.
- § 21.2.3 Continuous monitoring
$write : same as $display but doesn't terminate with a newline (\n)
- § 21.2.1 The display and write tasks

Example:

reg [3:0] a,b;
integer i;
initial begin
  $monitor("monitor a:%h b:%h @ %0t", a, b, $time);
  for(i=0; i<4; i=i+1) begin
    $strobe("strobe  a:%h b:%h @ %0t", a, b, $time);
    $display("display a:%h b:%h @ %0t", a, b, $time);
    case(i)
      0 : a = 4;
      1 : b = 1;
      2 : begin end // do nothing
      3 : {a,b} = 9;
    endcase
    $display("display a:%h b:%h @ %0t", a, b, $time);
    #1;
  end
end

Outputs: (notice the print order and that monitor is not displayed at time 2)

display a:x b:x @ 0
display a:4 b:x @ 0
monitor a:4 b:x @ 0
strobe a:4 b:x @ 0
display a:4 b:x @ 1
display a:4 b:1 @ 1
monitor a:4 b:1 @ 1
strobe a:4 b:1 @ 1
display a:4 b:1 @ 2
display a:4 b:1 @ 2
strobe a:4 b:1 @ 2
display a:4 b:1 @ 3
display a:0 b:9 @ 3
monitor a:0 b:9 @ 3
strobe a:0 b:9 @ 3