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system-veriloguvm

do_compare has a result of 1 however .compare return value is 0

I'm following http://cluelogic.com/2013/01/uvm-tutorial-for-candy-lovers-do-hooks/ and https://verificationacademy.com/cookbook/transaction/methods to implement compare the only difference is instead of big logical AND (&&) I'm using

virtual function bit do_compare ....
  do_compare &= <statement A>;
  do_compare &= <statement B>;

  $display (do_compare); ///< this displays 1
  return do_compare;

endfunction

However returned value always comes out to be 0 for e.g. consider sequences

temp = m.compare(n);
$display (temp); ///< displays 0

I've been trying to debug why temp is always 0 but couldn't figure out. Can anyone point me in right direction

Solution

  • Having a look in the source code for compare(...) I see the following condition for do_compare(...) to be called:

    if(!done) begin
  comparer.compare_map.set(rhs, this);
  __m_uvm_field_automation(rhs, UVM_COMPARE, "");
  dc = do_compare(rhs, comparer);
end

    Not really sure when they set done (one case is when an error is flagged for fields that are automated with the field macros). Are you sure your do_compare(...) is being called? Add a `uvm_info in there or set a break point to make sure.

    Another idea I saw in a presentation from John Aynsley is to not use the field automation macros if you want to implement your own do_* methods. In case you are using them, try setting all fields to UVM_NOCOMPARE. This is because the return value of compare(...) is computed as return (comparer.result == 0 && dc == 1);. This means that even if your do_compare(...) returns 1, it may still be the case that one of the automated fields flagged an error (although I would have expected an error message).