Xilinx Vivado 2023 IP block design issue: Unable to connect output of RTL module to AXI GPIO output that is connected to LED

Question

I am using Vivado 2023.1, and I am not able to connect the output of the RTL module to the AXI GPIO output that is connected to the LED. Please take a look at the attachment. RTL is below

module led_blinker (
    input wire sysclk,
    input wire rst,
    output reg led
);

    reg [26:0] counter;
    reg led_state;

    

//TO make reset signal work with PS, make sure it is negedge reset
    always @(posedge sysclk or negedge rst) begin
        if (~rst) begin
            counter <= 27'd0;
            led_state <= 1'b0;
        end else begin
            if (counter == 27'd99999999) begin  // Adjust for desired blink rate
                counter <= 27'd0;
                led_state <= ~led_state;
            end else begin
                counter <= counter + 1'b1;
            end
        end
    end

        always @(*)
     begin
        led = led_state;
    end

endmodule

Answer 1

You can't connect two outputs together. It has to be output to input.