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verilogsystem-verilog

Compile error in define macro when using $bits

While writing the following macro, I am getting the compile error:

`define TEST1(out, in, sel)      \ \
  integer i;                      \ \
  always_comb begin                  \ \
    out = $bits(1'b0);               \\

    for(i=0; i<=$bits(sel); i=i+1)   \\
        out = out | ({$bits(out){sel[i]}} & in[i]);    \\
    end          ;

Error-msg:

near "[": syntax error, unexpected '[', expecting ',' or '}'.
Solution

  • Remove the blank line, and only use one backslash per line. Refer to IEEE Std 1800-2017, section 22.5.1 `define:

    If more than one line is necessary to specify the text, the newline character shall be preceded by a backslash ( \ ). The first newline character not preceded by a backslash shall end the macro text.

    `define TEST1(out, in, sel)      \
  integer i;                      \
  always_comb begin                  \
    out = $bits(1'b0);               \
    for(i=0; i<=$bits(sel); i=i+1)   \
        out = out | ({$bits(out){sel[i]}} & in[i]);    \
    end          ;