system-verilog system-verilog-assertions cadence

Do System Verilog coverpoints and covergroups work for real variable types?

I'm looking into using coverpoints and covergroups for mixed signal verification in Cadence to verify some constrained random classes I've written. However, I haven't been able to find online if coverpoints can be used for reals. In fact, I've found some older articles saying they're not supported. Can coverpoints be used to verify reals and if so what additional syntax in necessary?

Solution

No. The SystemVerilog LRM section 19.5 says

A coverage point specifies an integral expression that is to be covered.

The bin structure of coverpoint is defined using equality operations, which real numbers has problems with approximation.

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