How to use parameterized bitwidth for a constant value in Verilog?

Question

Consider the following example:

parameter BITWIDTH = 16;

This works:

logic [1:0][BITWIDTH-1:0] var = {16'h30, 16'h40};

This doesn't work:

logic [1:0][BITWIDTH-1:0] var = {BITWIDTH'h30, BITWIDTH'h40}; 

How can I use parameters in the above line of code?

Answer 1

SystemVerilog will resize numeric literals to the correct size following well-defined rules so its not necessary to define the size:

logic [1:0][BITWIDTH-1:0] x = '{'h30, 'h40};

However, some tools do throw warnings so you can cast the literal to the right size like so:

logic [1:0][BITWIDTH-1:0] x = '{BITWIDTH'('h30), BITWIDTH'('h40)};