Does the following style of coding makes any difference while synthesis?

Question

I am trying to implement a module in my project for which i need the final value to be stable for a while, hence implemented as below. both of them are showing the same result in simulation. will the tool generate same hardware or different one?

always @(posedge clk) begin
if(en)
    count <= count + 1;
else
  begin
    a <= count;
    count <= 0;
  end

if(count == 0) b <= a;

end

what is the difference between above coding style and the one below? Does it make any difference while synthesis?

always @(posedge clk) begin
    if(en)
        count <= count + 1;
    else
      begin
        a <= count;
        count <= 0;
      end
end 

always @(posedge clk) begin
    if(count == 0)
        b <= a;
end

And I am using Vivado 2015.4 tool for synthesis.

Answer 1

It will generate the same hardware output. It doesn't matter if you split clocked statements into one or multiple always-statements, as long as they are functionally identical.