And when the synthesis is completed i am getting many files like .fw, .mcs, .prm along with .bit file, and can we dump those other files other than .bit file into FPGA? Which one is more advantageous project mode or non project mode? Coding is done in verilog.
The best explanation is probably found in the Xilinx document UG892 which can be downloaded from their website. Chapter 2 Page 18 gives the details:
Essentially in project mode you add files which get copied into a new directory structure, set options and setup the synthesis/place&route runs that you need and then Vivado manages the acutal commands run. It's more of a push button flow in the IDE, but can also be scripted (again all the setup is at the front end and then you essentially say 'go' and it works out what it needs to do).
In the non-project flow you get complete control over the compilation process (no copying of files, they're just used from the location you give) and the synthesis process and manage all the settings and the commands that are run yourself. It requires a knowledge of TCL to write the scripts, but there are example flows in the documentation.
We use the non-project flow as it doesn't use an binary project files and is entirely scripted from TCL and Makefiles (which is not integral to the way Vivado works, but makes our life so much easier). While a bit trickier to set up, it gives you more control, allows you to checkpoint the design at any point and it is easier to put into a version control system, so you can track changes in constraints and build options.