Verilog: Is the following code going to make a race condition?

Question

I'm trying to make a pipeline processor using Verilog HDL. I realized that there are maybe some race conditions somewhere in my code. So I'm going to write a sudo code and would like to ask you about if there is a race condition within and how to avoid it :

module A(input wire reset, input wire clock, output reg a_reg_o);
   always @(posedge clock)
   begin
      if(reset == 1'h1)
      begin
         a_reg_o = 1'h0;
      end
      else
      begin
         a_reg_o = 1'h1;
      end
   end
endmodule

module B(input wire reset, input wire clock, input a_i);
   reg b;

   always @(posedge clock)
   begin
      if(reset == 1'h1)
      begin
         b = 1'h0;
      end
      else
      begin
         if(a_i == 1'h1)
         begin
            b = 1'h1;
         end
         else
         begin
            b = 1'h0;
         end
      end
   end
endmodule

module Main(input wire reset, input wire clock);
   wire a_o;
   A a(reset, clock, a_o);
   B b(reset, clock, a_o)
endmodule

So imagine I trigger reset signal. After the first positive edge of clock the register a_reg_o is going to be 0 and register b from module B also is going to be 0 (No race conditions yet). Now I release the reset button and let it to be negative. On the next positive edge of the clock the register a_reg_o is going to be 1, but what about register b from module B ? Is it going to be : 1. Zero, Because it didn't see the a_i changes yet. 2. It depends on the modules (A and B) total delay ( i.e. a race condition).

Thank you.

Answer 1

This is why there a non-blocking (NBA) assignments in Verilog. The coding rule is whenever there are multiple processes (in this case, multiple always blocks) accessing the same signal (a_o) synchronized to the same event (@posdege clock) where one process writes and another process reads, you need to use and NBA <= assignment to write to the signal.