Search code examples
verilogxilinxfifosynthesis

Parameterized FIFO instantiation in Verilog

I wanted to have a parameterized FIFO instantiation so that I can call a single FIFO instance with change in depth(parameter).

e.g. I have written a code for FIFO with depth as a parameter.

I will know the depth of the FIFO only by the configuration from Microprocessor. Based on the register configuration, can i call this FIFO with variable parameter like value? 

integer depth_param;
 if(config_reg[1])
   depth_param <= 128;
 else
   depth_param <= 512;

 genfifo #(depth_param) (.din (din),.wr(wr)....);

fifo module is:

 module gen_fifo #(depth = 128)
 ( din,wr,rd,clk....);

can you please suggest is there a way I can do this?

Solution

  • This is what the LRM says:

    Parameters represent constants; hence, it is illegal to modify their value at run time. However, module parameters can be modified at compilation time to have values that are different from those specified in the declaration assignment. This allows customization of module instances. A parameter can be modified with the defparam statement or in the module instance statement. Typical uses of parameters are to specify delays and width of variables.

    'run time' means during simulation, after elaboration. A synthesiser doesn't 'run' anything, but what you're doing is effectively "run time", and so is illegal.

    This doesn't mean that you can't do it, though. Pass in your FIFO depth as a module port. I'm assuming that you know how to code a FIFO from first principles. If so, you will normally have a constant for the FIFO size; just replace this constant with the value at the port, and find some way to set the memory size. You'll obviously need to be careful when changing the FIFO size - you may need to reset it, for example. If you don't know how to code a FIFO you should ask with an FPGA or an electronics tag.