I am trying to use a for loop with dynamic variable to store elements in an array. But when I synthesize the code it gives me an error for dynamic variable. Here is the code which works fine in modelsim. Since its just a simultor but I want to download this code on a FPGA target device.
`define LENGTH 16 //length of array elements
`define WIDTH 8 //width of element in array
module multi;
integer i,j,k,f,l,n=0;
integer r=0;
integer c;
reg [`WIDTH-1:0] reuse [0:(`LENGTH/2)-1];
reg [`WIDTH-1:0] local [0:`LENGTH-1];
reg [`WIDTH-1:0] arr [0:`LENGTH-1];
initial
begin
$readmemh("block.txt", arr);
for(i=0;i<`LENGTH;i=i+1)begin
c=0;
for(l=0;l<r;l=l+1)begin
if(reuse[l] ==arr[i])begin
c=c+1;
end
end
if(c==0)begin
f=0;
for(j=0;j<n;j=j+1)begin
if(local[j]==arr[i])begin
reuse[r]=arr[i];
r=r+1;
f=1;
for(k=j;k<n-1;k=k+1)begin
local[k]=local[k+1];
end
local[n-1]=4'hx;
n=n-1;
end
end
if(f==0)begin
local[n]=arr[i];
n=n+1;
end
end
end
$display("reuse:");
for (i=0; i < (`LENGTH/2); i=i+1)
$display("%d:%h",i,reuse[i]);
$display("local:");
for (i=0; i < `LENGTH; i=i+1)
$display("%d:%h",i,local[i]);
end
endmodule
There is a key difference between writing behavioral Verilog code and RTL Verilog code (i.e. synthesizable code that will be implemented in an ASIC or FPGA). The important thing for RTL is to remember that you are using Verilog as a hardware description language, not simply another alternative to C or the multitude of other programming languages. So you need to have in mind what kind of hardware you are trying to describe. Real hardware modules and chips have inputs and outputs, so you have to specify those. If you don't have any outputs, the logic synthesizer will happily optimize away all your code because the module doesn't need any of it if there is now output. So you need to specify the I/O.
You don't need to worry about logic reduction and Karnaugh maps; the synthesis engine will do that kind of optimization on the combinatorial logic for you. But you should have some idea of what kind of storage you are trying to implement (registers, latches, RAM, ROM) and how the clouds of combinatorial logic will hook up to it. All synchronous logic requires requires clocks to drive those memory elements. You should have some plan for how the results of each stage of logic get pipelined through your design, even if just a rough sketch. Synchronous logic needs to be defined inside an "always" block with the clock in the sensitivity list. Initial blocks are generally not used for hardware (exception: some FPGAs allow you to use initial blocks to specify the power on condition of RAMs, something that can't be done with ASICs).
Finally real hardware doesn't come and go. You can create a paramaterized module that implements just enough logic for a particular function, but you can't change the amount of logic in existence at run time like you are trying to do in this code. Parameterized structures are allowed in RTL, dynamic structures are not since there is no way to create new logic once the design has been synthesized. If you need to have something change size on the fly, then you would have to code up the largest design you need and selectively use subsections of it while running.