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Xilinx loop has iterated 64 times error

I am writing code for a pipeline multiplication algorithm and while synthesizing using xilinx 10.1, I am getting the following error:

"ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more".

How can I fix it or how can I find out what causes it?

Solution

  • Based on information from Xilinx webpage:

    This error occurs if XST encounters a loop (typically a "while loop") that does not have a discrete termination. Rather than unrolling the loop forever, XST fails with this error during HDL analysis. A line number is not provided, but the error is reported within the context of the entity/module that is being analyzed.

    You can solve that issue by adding e.g. set -loop_iteration_limit 256 to .xst file in your project. Additional information you can find here.