Quartus II : can't determine definition of operator ""<=""

Question

I am stucked with some VHDL code.

I am trying to compile this:

entity ball is
    port(video_on : in std_logic;
        pixel_x,pixel_y : in std_logic_vector(10 downto 0);
        obj3_r,obj3_g,obj3_b : out std_logic_vector (3 downto 0);
        obj3_on : out std_logic);
end entity;

architecture arch of ball is


-- definimos dimension de izquierda a derecha
constant ball_l : integer :=800;
constant ball_r : integer :=815;

-- definimos dimension de arriba a abajo
constant ball_top : integer :=502;
constant ball_bottom : integer :=522;


begin

obj3_on <= '1' when (ball_l <=pixel_x) and (pixel_x <= ball_r) and (ball_top <= pixel_y) and (pixel_y <= ball_bottom) else 
            '0';

obj3_r <= (others => '0');
obj3_g <= "0111";
obj3_b <= (others => '0');

end arch;

Quartus II is showing this error : can't determine definition of operator "<="; at the line where the WHEN STATEMENT is used. I have no idea what the problem is.

Thanks for your help!!

Answer 1

You are trying to use relational operators on signals of type std_logic_vector which doesn't have them defined. You can make it work by one of the following:

• Use the unsigned type defined in ieee.numeric_std. It is the standard way to interpret arrays in a numeric context. Either declare your port signals as unsigned or use the type conversion functions in each comparison.

• With VHDL-2008 support, use the ieee.numeric_std_unsigned package which adds unsigned numeric semantics to std_logic_vector.

Don't use the non-standard std_logic_arith which is an earlier package similar to numeric_std_unsigned.

You should also use natural instead of integer for the constants since there is no operator defined for comparing unsigned with integer.