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fpgapci-e

PCIe BAR access

I have a FPGA card plugged in to a host memory over PCIe. I want my host to access 2GB of DDR memory on card. Does that mean I'll have to request for a BAR size of 2GB ?

My understanding is that, if I request for a 32KB of address space and if host assigns it as 0x0f03_0000, then, it can access upto 0x0f03_7FFF. So read/write request issued by host in this range would end up on my card.

Solution

  • Does that mean I'll have to request for a BAR size of 2GB ?

    In most systems you can't request so much memory for a BAR.

    With the i.MX6 PCIe for example the maximum memory assigned to BAR PCIe is 15MB.

    To access a large amount of memory you will need to add memory controller in FPGA to split memory space.

    My understanding is that, if I request for a 32KB of address space and if host assigns it as 0x0f03_0000, then, it can access upto 0x0f03_7FFF. So read/write request issued by host in this range would end up on my card.

    Yes, exactly.