In C, you can do this:
int a[5] = {1, 2, 3, 4, 5};
On VHDL, I need to do about the same thing in a function. Now it looks like this:
type rom_type is array (0 to 1) of std_logic_vector(1 downto 0);
function get_rom return rom_type is
variable rom: rom_type;
begin
rom(0) := "10";
rom(1) := "01";
return rom;
end;
Is there a way to make the array filling the same as in c? Something like this:
rom := {"10", "01"};
Yes
rom := ("10", "01");