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verilogfpgaquartusintel-fpga

Quartus-FPGA: Disable Path Optimization

module path1(out, in, w0, w1, w2, w3, w4, w5, w6, w7, w8, w9);
input in;
output out;

output w0, w1, w2, w3, w4, w5, w6, w7, w8, w9;

not(w0, in);
not(w1, w0);
not(w2, w1);
not(w3, w2);
not(w4, w3);
not(w5, w4);
not(w6, w5);
not(w7, w6);
not(w8, w7);
not(out, w8);
endmodule

Hello. I have a module like this. What it does is basically delaying the output. I want it to cause delay in my FPGA hardware.

enter image description here

But when I checked the RTL Viewer, I saw that Quartus optimized the path and it no longer works as I wanted. The output is directly connected to input instead of having 10 NOT gates between them. I assigned all wires as outputs but that didn't help as well.

enter image description here

I researched to disable optimizations and found some options in Fitter Settings. As you can see, I disabled optimization related things but it didn't work as well.

I have also tried implementing the path with LCEEL Primitives but that didn't cause any delay and even showed as nothing but a straight bus in the RTL Viewer.

What can I do to create such a path? Is it even possible to disable such optimization?

Solution

  • Today I finally got some expected results. Seems like the keyword

    (* keep = 1 *) wire intermediateLine;

    works to disable optimization.