How many addition operations can be performed instead of a single multiplication on FPGA? In terms of used resources - as an example - energy and logic area cost. I would like to know it for multiple precisions. I know that for FIX16 - single multiplication takes 15x times more resources than a single addition. For FP32 - it's 4x to 1. The FPGAs are different and I would like to understand more general estimation. If specific, I'm trying to rely on this chip (https://www.digikey.com/en/products/detail/amd/XCVC1902-2MSEVSVA2197/15907949). If possible, somebody can point me in the direction of where to find those specs or how to estimate the values based on data sheets.
Thanks.
In FPGAs, a multiplier/addition operation can happen in either of two ways a) using built in dsp block OR b) using CLB resources.
Lets consider the first case: each dsp can implement one multiplication operation but the number of addition depend on the architecture of the DSP engine. Let see what do data sheet of the said FPGA has to say about it:
Each DSP Engine fundamentally consists of a dedicated 27 × 24 bit twos complement multiplier and a 58-bit accumulator. The multiplier can be dynamically bypassed, and two 58-bit inputs can feed a single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions of the two operands.
So in short, it can either implement 2 24-bit additions or 4 12-bit additions.
When multiplication is implemented in CLB, the situation becomes difficult. Now it depends on at-least two factors:
Now the corresponding number of additions again depended on at-least the same two factor. But I don't have much knowledge about CLB usage of additions and you may have to wait until some one describes a more concise answer.