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verilogfpgaxilinx

optimization choices with slice LUT and slice registers in Xilinx FPGA

Has anybody has any idea, that in Xilinx FPGAs when Slice LUTs are used and Slice Registers are used? What are the various design choices that one can have to explicitly target one of these particular resources.

Solution

  • LUT's have no state and are used to implement combinatorial logic
    assign x = a + b;

    Registers are just elements that hold state, and do not implement any logic
    always @(posedge clk) state_f <= state_nxt;

    If you want to target one or the other, then you have to choose your algorithms to either minimize combinatorial logic or minimize state.

    I think this is the question you are asking, my apologies if it is too simple of an answer.