RTL simulation vs Delta cycle simulation

Question

Could some one please elaborate on ​"RTL simulation is faster than delta-cycle simulation but can not be used in all situations"? I don't know what Delta cycle simulation

Answer 1

In a Verilog simulation delta-cycles are those used by the simulator to calculate the next value.

When entering a combinatorial section the simulator will use many delta cycles to resolve the dependencies required for the answer. If you have combinatorial loops not broken up with a flip-flop the simulator may get stuck constantly reiterating the loop trying to resolve the dependencies, which is impossible due to the loop. If you get a simulation which just hangs this is often the cause.

The non-blocking assignment (<=) makes use of delta-cycles, by resolving the right hand side values (potentially many delta-cycles), then a delta cycle later assign these to the left hand side.

a<=b;
b<=a;

In the simple case above b and a are copied to temporary location (think next_a next_b). Then a delta cycle later a is assigned to next_a and b to next_b.

There are other ZERO-Time constructs which do not use a delta cycles often used in Test benches for modelling. I have no experience of these hopefully another answer could describe there use.