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How to generate sinc wave using verilog

I'm making an "Arbitrary waveform generator" on FPGA. currently, I'm working on generating "sinc" wave using FPGA [using verilog].

For a fixed frequency, I can make the sinc using LUT on a ROM, but I need to give the option to make sinc of user-defined frequency.

So, any good idea how to make it???

Any help would be highly appreciated.

Solution

  • You can still use a LUT for the variable frequency sin(x) function.

    Just generate a LUT of 1000 or so (depending on your desired resolution) entries of a single cycle of a sine wave. Then you decide how many entries to jump through each clock cycle based on the desired frequency.

    As an example, if your clock is 1MHz, and the desired output frequency is 1KHz, then you step to the next LUT entry every clock (complete the period in 1000 clock cycles). If the desired output frequency is 10KHz, then you jump 10 entries in the LUT every cycle. (complete the period in 100 clock cycles)

    To get the sinc though sin(x)/x, I think you will need to implement a division circuit, as I can't think of any way around that.