Arithmetic Right Shift in Verilog

As part of a processor design, I am implementing a simple behavioral right shifter using Verilog.

The shifter inputs a 32 bit variable and outputs either a right logical shift or a right arithmetic shift based on a variable (input) choice.

Following is the code:

 module ShiftRight(
  input signed[31:0] inp,
  input [31:0] shamt,
  output [31:0] out,
  input choice
  );

  assign out = (choice)? (inp>>>shamt):(inp>>shamt);


 endmodule

This results in a correct behavioral implementation but gives the following warning during synthesis:

Unit ShiftRight : the following signal(s) form a combinatorial loop: out_shift0000<31>.

(the coeff in brackets is basically the most significant bit of inp, 31 in my case). So I was wondering whether this had anything to do with inp bein signed.

Solution

I'll guess your synthesizer is just exploding at the thought of having to arithmetic shift a vector by 2^32 bits (4,294,967,296), and in it's internal RTL to gates synthesis it's ending up in a circular loop.

Since I'm guessing you don't need to shift by 4 billion bits, maybe you could use a reasonable number for your shift amount?