cpu-architecture Examples and Free Source Code

RISC-V architecture, why do one add 4 bytes with no branch but shift with one when branch?...

assembly cpu-architecture riscv program-counter risc

Why is Pipelined Processor identified as a SISD?...

pipeline cpu-architecture processor

Assembly: why some x86 opcodes are invalid in x64?...

assembly x86 x86-64 cpu-architecture opcode

Does processor stall during cache coherence operation...

multithreading caching cpu-architecture cpu-cache

MSI: Why do we need to write the line back when other CPU is going to override it?...

cpu-architecture cpu-cache

What is the difference between physical and logical cores in a CPU/microprocessor?...

cpu-architecture terminology processor hyperthreading cpu-cores

Why does std::atomic_compare_exchange update the expected value?...

c++multithreading cpu-architecture atomic compare-and-swap

Skipping store queue searches in Gem5 when issuing loads causes crashes in guest...

c++cpu-architecture gem5

Why is the JVM stack-based and the Dalvik VM register-based?...

jvm dalvik cpu-registers cpu-architecture vm-implementation

Can modern x86 CPUs do ideal out of order execution?...

assembly x86 cpu-architecture low-level superscalar

Can a TLB hit lead to page fault in memory?...

memory-management operating-system kernel cpu-architecture tlb

Microcode emulator in Python...

cpu cpu-architecture

What is the purpose of using $0 as destination in MIPS...

mips cpu-architecture

Load/stores per cycle for recent CPU architecture generations...

performance x86 cpu cpu-architecture memory-bandwidth

Can modern CPUs run in SIMT mode like a GPU?...

multithreading gpu cpu cpu-architecture

Significant speed difference between two seemingly-equivalent methods of calculating prefix sums wit...

c++performance assembly gcc cpu-architecture

how long is a memory address typically in bits...

memory byte cpu-word cpu-architecture processor

Is there a max size to MIPS static data segment?...

memory mips cpu-architecture mips32

What exactly is a dual-issue processor?...

embedded arm pipeline cpu-architecture

VIPT Cache: Connection between TLB & Cache?...

caching cpu-architecture cpu-cache tlb mmu

Is x86_64 IDT shared between CPUs in Linux kernel?...

linux linux-kernel x86-64 cpu-architecture interrupt

What's the difference between dispatching and issuing in CPU pipeline...

x86 cpu cpu-architecture intel amd-processor

How to match the microarchitectural values produced in the pipeline with its corresponding architect...

simulation cpu-architecture riscv processor

Why there is different register address for sstatus an mstatus although they are different view of s...

cpu-architecture privileges riscv instruction-set

Which execution unit in the CPU executes the prefetch instruction?...

cpu cpu-architecture prefetch

forwarding data in which stage in mips piplined...

verilog mips pipeline cpu-architecture mips32

Why 32-bit processor can only address 4GiB of memory, even with large word size?...

cpu-architecture memory-address processor addressing program-counter

How to use memory barriers (instead of fetch_add) to make addition atomic and thread safe...

c++cpu-architecture atomic memory-barriers stdatomic

How does the memory controller guarantee memory ordering of atomics when propagating cachelines?...

c++cpu-architecture atomic stdatomic memory-model

Branch prediction and UB (undefined behavior)...

c++c cpu-architecture undefined-behavior branch-prediction