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Why gcc -O0 allocating extra space for local variable (16 instead of 8 bytes)?...


cassemblygccx86stack-memory

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x86 NASM Crash - Iterate over string...


assemblyx86nasmcalling-convention

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Why do x86 FP compares set CF like unsigned integers, instead of using signed conditions?...


assemblyx86ssesse2x87

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Does FADDP ST(0), ST(1) make sense?...


assemblyx86instruction-setx87

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Assembly Language equivalent to Ceil , Floor...


assemblyx86floorceilx87

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change floating-point operation in x86 system to the one in armv8 system...


floating-pointx86stackarminline-assembly

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WinDBG under VMware Workstation Pro 16.2.3 zeros x87 FPUInstructionPointer when single-stepping...


assemblyx86shellcodefpux87

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Cube root on x87 FPU using Newton-Raphson method...


assemblyx86masmnewtons-methodx87

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What do the letters in port usage on uops.info mean?...


x86cpucpu-architectureintel

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What is the benefit of calling ioread functions when using memory mapped IO...


linuxiolinux-kernelx86linux-device-driver

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How does stack memory will be use to store cpu state during interrupt?...


assemblyx86x86-64interruptosdev

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What is the inverse of "_mm256_cvtepi16_epi32"...


x86g++intrinsicsavxavx2

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Performance penalty: denormalized numbers versus branch mis-predictions...


c++x86floating-pointmicro-optimizationbranch-prediction

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Assembly: Character type checking...


assemblyx86characterbitwise-operators

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If cache invalidation happens every time memory mappings change, why not opt for VIVT?...


cachingx86cpucpu-architecturecpu-cache

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Assembly: calculation of string index...


arraysstringloopsassemblyx86

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Printing decimal number in assembly language?...


assemblyx86outputdecimal

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Can addition be done in less than a cycle when outputs depend on each other?...


assemblyx86cpu-architectureintel

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Would compiler put jump table at the end of function?...


cassemblygccx86

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Cross compile arm assembly for x86...


assemblyx86armclang

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How do modern Intel x86 CPUs implement the total order over stores...


x86intelcpu-architecturememory-barriersmesi

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Push the address of something+constant in NASM? Why is LEA required?...


assemblyx86nasm

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Intel VT-x: How do I trigger posted interrupt processing on the same core?...


x86intelinterruptvirtualizationhypervisor

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Difference between low and high 8-bit registers; do their values use bits in opposite bit-endian ord...


x86cpu-architecturecpu-registers

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x86 division exception-return address...


assemblyx86virtualboxx86-16interrupt-handling

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Was there any advantage to the 386 architecture making 16-bit register arithmetic leave upper bits u...


assemblyx86cpu-architecturehardwarecpu-registers

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Was there a P4 model with double-pumped 64-bit operations?...


x86x86-64intelcpu-architecture

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Atomicity of loads and stores on x86...


c++x86cpu-architectureatomicmemory-barriers

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Memory Model in C++ : sequential consistency and atomicity...


c++multithreadingc++11x86stdatomic

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Will memory write be visible after sending an IPI on x86?...


assemblyx86operating-systemmemory-barriersmsr

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