cpu-architecture Examples and Free Source Code

Multi-Level Cache Performance...

cpu computer-science cpu-architecture cpu-cache

Why does B 25 or BEQ 25 in ARM assembly language mean "go to PC + 8 + 100"...

assembly arm branch cpu-architecture machine-code

Is processor can do memory and arithmetic operation at the same time?...

assembly x86 cpu-architecture

Out-of-order instruction execution: is commit order preserved?...

cpu cpu-architecture instructions pipelining dynamic-execution

Reasons a C Compiler Ignores register Declaration...

c compiler-construction compiler-optimization cpu-architecture cpu-registers

RISC-V: Why set least significant bit to zero in JALR...

cpu-architecture riscv

How does MIPS I handle branching on the previous ALU instruction without stalling?...

assembly mips pipeline cpu-architecture

Why are CISC processors harder to pipeline? In what sense are some instructions "more complex&q...

x86 cpu-architecture instruction-set pipelining

Cache Implementation in Pipelined Processor...

mips cpu-architecture cpu-cache

What is the simplest Turing complete CPU instruction set which can execute code from ROM?...

cpu cpu-architecture instruction-set turing-complete

What could cause an extra bit to be added to a result in a non-blocking assignment?...

verilog cpu-architecture xilinx

Why does MIPS use one delay slot instead of two?...

mips cpu-architecture instruction-set

How do I know whether I'm looking at a CISC or RISC instruction set?...

cpu-architecture instruction-set

sequence of branch taken or not-taken that reduces the branch misprediction rate...

mips pipeline cpu-architecture branch-prediction

Can out-of-order execution lead to speculative memory accesses?...

x86 arm cpu-architecture powerpc sparc

Invalid results querying my system’s cache information with GetLogicalProcessorInformation()...

c++winapi x86 cpu-architecture cpu-cache

Why isn't there a data bus which is as wide as the cache line size?...

caching memory cpu-architecture cpu-cache micro-architecture

How to design a virtual cpu / instruction set: distinguish LDA $02 from LDA B...

assembly cpu-architecture machine-code instruction-set immediate-operand

What enforces memory protection in an OS?...

assembly memory operating-system cpu-architecture mmu

How does Java Handle Endianess when running on Little Endian CPU Architectures?...

java performance cpu-architecture endianness openj9

GCC inclusion of AVX512's "Fused Multiply Add" instructions when compiling for Cascade...

gcc intel cpu-architecture avx512 fma

Does memory fencing blocks threads in multi-core CPUs?...

multithreading x86 cpu-architecture multicore memory-barriers

What does memory_order_consume really do?...

c++cpu-architecture lock-free memory-model stdatomic

How does DC PMM (memory mode) cache coherence behave?...

x86 intel cpu-architecture cpu-cache persistent-memory

Why doesn't there exists a subi opcode for MIPS?...

assembly mips cpu-architecture instructions instruction-set

Are snoop requests sent to all the cores in a multi node setup?...

x86 intel cpu-architecture cpu-cache

Is there any way to find the Instruction Set of an undocumented processor?...

assembly reverse-engineering cpu-architecture instruction-set

How to simplify circuits...

logic computer-science cpu-architecture circuit digital-logic

Are Harvard architecture computers immune to arbitrary code injection and execution attacks?...

security cpu-architecture harvard-architecture

is the address bus indicate the size of the address in ram?...

memory cpu-architecture