cpu-architecture Examples and Free Source Code

Would an Instruction Set Architecture benefit from both an ADC and SBC, or could all carry instructi...

assembly cpu-architecture instruction-set carryflag

Temporality of ST64B and MOVDIR64B...

assembly x86-64 cpu-architecture arm64 micro-architecture

Why does ARM have 16 registers?...

arm cpu-registers cpu-architecture

How do instructions from a program get sent to different memory levels? Are they pre-loaded when the...

assembly memory cpu cpu-architecture instructions

Which alignment causes this performance difference...

performance x86 cpu-architecture memory-alignment perf

Adding a redundant assignment speeds up code when compiled without optimization...

performance assembly x86 cpu-architecture micro-architecture

Invalidation of the cache from L1 cache...

x86 intel cpu-architecture cpu-cache cache-invalidation

What happens if two cores try to write to same place in main memory at same time?...

linux multithreading concurrency cpu-architecture

How does data get into the General Purpose and other registers so that the CPU can use it for comput...

assembly cpu-architecture cpu-registers

How is execution resumed after a hardware breakpoint without an infinite loop?...

debugging gdb cpu-architecture breakpoints

What is the minimum number of addressing modes necessary for computation?...

assembly x86 cpu-registers cpu-architecture addressing

Instruction Pointer vs Program Counter?...

assembly cpu cpu-architecture cpu-registers program-counter

Why place of Mem[MA] in MB then copy from MB to IR rather than going straight from Mem[MA] to IR?...

cpu-architecture hardware

What if the processor does not have special instructions for input and output...

assembly io cpu-architecture

Write buffers performance for write-back or write-through policy...

caching cpu-architecture cpu-cache

Understanding how EIP (RIP) register works?...

assembly x86 gdb cpu-registers cpu-architecture

Does a Length-Changing Prefix (LCP) incur a stall on a simple x86_64 instruction?...

performance assembly x86-64 cpu-architecture micro-optimization

Why does the short (16-bit) variable mov a value to a register and store that, unlike other widths?...

c assembly x86 cpu-architecture micro-optimization

Software initialization code at 0xFFFFFFF0H...

x86 operating-system cpu-architecture boot bios

Do I need to externally call flush if using cuda api to copy from GPU Memory to Persistent Memory?...

cuda cpu-architecture flush persistent-memory clflush

On x86-64, is the “movnti” or "movntdq" instruction atomic when system crash?...

x86-64 atomic cpu-architecture sse persistent-memory

What's the purpose of the rotate instructions (ROL, RCL on x86)?...

assembly x86 cpu-architecture bit-shift instruction-set

A question about Interrupt cycle FGI and FGO flipflops conditions - Basic Computer Organization and ...

cpu-architecture

Completely simultaneous execution of two instructions (RISCV)...

pipeline cpu-architecture riscv

How does a CPU handle asynchronous interrupts?...

x86 arm interrupt cpu-architecture

What memory address spaces are there?...

c cpu-architecture memory-address

Thread synchronization: How to guarantee visibility of writes...

synchronization thread-safety cpu-architecture memory-barriers memory-model

Moving binary files between big endian and little endian platforms...

network-programming cpu-architecture endianness

Program counter error while implement single cycle mips processor...

verilog cpu-architecture fpga

ARM endianness and byte ordering for .ascii vs .word...

assembly arm cpu-architecture endianness