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Assembly function's data arrangment in data section...

assemblyx86-64cpu-architecturemicro-optimization

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Delay in atomic variable update reflection across threads...

c++multithreadingcpu-architectureatomicmicrobenchmark

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How are the bytecodes for MIPS nop and sll differentiated?...

assemblymipscpu-architectureinstruction-setno-op

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Is fdiv faster with a dword or qword argument?...

assemblyx86floating-pointcpu-architecturex87

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Why does Intel use a VIPT cache and not VIVT or PIPT?...

cachingmemoryintelcpu-architecturecpu-cache

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Are sempahores (sem_t) inside C structs padded to respect alignment?...

cstructcpu-architecturesemaphorememory-alignment

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How does an Arithmetic Logic Unit do comparisons?...

cpucpu-architecturealu

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What percentage of Android phones are little-endian?...

javaandroidcpu-architectureendianness

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Does Zen 4 core have 48 flops per cycle for 32-bit precision fp?...

performancex86-64cpu-architectureavx2amd-processor

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What's the difference between "Sub-NUMA Clustering" and "Hemisphere and Quadrant ...

cachingx86cpu-architectureintelnuma

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ADD slower than ADC in the first step of a bigint multiply on Coffee Lake (Skylake)...

performanceassemblyx86cpu-architecturemicro-optimization

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Does CPU work only with two´s complement?...

mathcpucpu-architecturesubtractiontwos-complement

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Why do we need stalls even if branches can be determined?...

mipscpu-architecturebranch-predictionpipelining

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Does Intel Cache Allocation Technology allow hits from CPUs in one group on cache lines in another g...

cpucpu-architectureintelcpu-cache

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How are shifts implemented on the hardware level?...

cpucpu-architecturebit-shiftcircuitalu

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how this example in computer architecture is possible for main memory?...

memorycomputer-sciencecpu-architecture

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How to convert a CPU name to a string for -march & -mtune for MinGW?...

c++windowsgccmingwcpu-architecture

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Does each core have its own private set of registers?...

memorymemory-managementcpu-registerscpu-architecture

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Question of Arm performance related to register allocation...

performanceassemblycpu-architecturearm64

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HOW TO FORCEFULLY DISABLE intel_pstate? intel_pstate is enabled on reboot even with intel_pstate=dis...

linuxlinux-kernelcpuintelcpu-architecture

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AND + CMP or SHR + CMP?...

coptimizationcpu-architectureportabilitymicro-optimization

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When #GP is raised from v8086 mode does the processor push an error code on the ring0 stack?...

exceptionassemblyx86cpu-architectureosdev

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What exactly happens when a skylake CPU mispredicts a branch?...

x86intelcpu-architecturebranch-predictionspeculative-execution

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Does the last level cache see the PC?...

cpucpu-architectureintelcpu-cacheprefetch

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Are new CPU instructions frequently used? How is compatibility implemented?...

linuxwindowsx86x86-64cpu-architecture

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how to find instructions per cycle in a processor?...

computer-sciencecpu-architecture

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What is the purpose of the Parity Flag on a CPU?...

assemblycpu-architectureparityeflags

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Why data with smaller size than CPU word size need to be aligned at multiple of its size?...

cmemorycpu-architecturememory-alignment

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MIPS pipeline stages - what happens when an instruction doesn't need a stage, like MEM for ALU i...

assemblymipspipelinecpu-architecture

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Why doesn't Ice Lake have MOVDIRx like tremont? Do they already have better ones?...

assemblyx86intelcpu-architectureinstruction-set

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