Does each core have its own private set of registers?

Question

Looking at this Intel core i7 nehalem micro-architecture

it seems that each core has its own private Register File. So I have a couple of short questions, because I thought that there is only 1 set of registers not dependent on the number of cores.

• Does each core have its own private set of registers? (RAX, RBX, RSP and so on).
• Does each core have its own MMU and TLB? Not just one shared across all cores?

I know the questions are highly micro-architecture dependent but I think the majority of modern x64 Intel cpu's follow the same design principle.

Answer 1

Each core has its own set of registers, MMU, TLB, level 1 caches (data and instruction), level 2 cache (this depends on processor) etc. Cache Coherency is supported across cores via "QPI" and in the case of high end Core 7 and server-based processors like Xeon, Cache Coherency is supported across processors on a multi-processor mother board by exposing "QPI" on the external pins of those processors (for processors where multi-processor cache coherency is not supported, "QPI" is not "exposed").

Wiki article: Nehalem