Error (10170): Verilog HDL syntax error (59) near text: "posedge"; expecting an operand

Question

I am getting error at line 59. I tried to Google it, but I couldn't find anything. Here is my code:

always @(posedge clk or negedge nReset) begin
    if (minute_start_in == 1'b1) begin
        counter <= 0;
    end else if (nReset == 1'b0) begin
        counter <= 0;
        dcf_values <= 59'b0;
    end else if (posedge(clk) && (clk_en_1hz == 1'b1)) begin // Line 59
        dcf_values[counter] <= ~dcf_Signal_in;
        counter <= counter + 1;
    end;
end

Answer 1

You need to restructure your code so nReset has priority.

always @(posedge clk or negedge nReset)
    if (nReset == 1'b0) begin
        counter <= 0;
        dcf_values <= 59'b0;
    end else // must have been triggered by posedge clk
    if (minute_start_in == 1'b1) begin
        counter <= 0;
    end else if (clk_en_1hz == 1'b1)) begin 
        dcf_values[counter] <= ~dcf_Signal_in;
        counter <= counter + 1;
    end