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logicverilogdigitalsystem-verilog

bit vector range selection with runtime value in system verilog

Let's say I have a vector value[6:0] and an input vector input[3:0]. The problem is I want to set a number of bit in value vector to 1 base on value of input, e.g.:

input = 0011 (3 in dec) then value = 000111 (set 3 bits to 1)
input = 0101 (5 in dec) then value = 011111 (set 5 bits to 1)

As we can do this easy only when the value in constant, but here it is run-time change. Any ideas on solve this?

Solution

  • There's no need to select a range here.

    wire [3:0] input;
wire [7:0] shifted;
wire [6:0] value; //This can only hold 0 to 7

//Assign 2^input then subtract 1
assign shifted = 1'b1 << input;
assign value = shifted - 1;