Synchronizing Negative-Edge and Positive-Edge Triggered Flip-Flops in HDL

I'm working on a VLSI design using SystemVerilog, and I have doubts with the use of signals between negative-edge and positive-edge triggered flip-flops. I have a negative-edge triggered flip-flop (reg1), and another for a positive-edge triggered flip-flop (sum). I need to perform a calculation involving these signals, and I want to avoid using reg1 just like that, since there will be only have half of the period between the negedge and positive edge of the clock.

Pseudocode / example: (reg2 comes also from a neg-triggered module and reg3 from a positive triggered one)

module somemodule ( ... );
   always @(negedge clk) begin
      reg1 <= reg2;
   end

   always @(posedge clk) begin
      sum <= reg3 + reg1;
   end
endmodule

The problem is that reg1 is updated on the negative edge of the clock, and sum is updated on the positive edge. I foresee that this mismatch might cause timing issues.

Could someone provide guidance on how to properly synchronize these signals and perform the calculation without encountering timing problems? Any insights, code examples, or best practices would be greatly appreciated.

Additional Context:

I've considered using a two-stage synchronization approach for reg1 before using it in the sum calculation, as well as using a flag to manage synchronisation. However, I'm not sure about the best way to proceed.
I would like to avoid using a higher frequency clock (double the freq).
Data is coming clocked like this from Analog domain.
This design will be synthesised in an advanced node. There are both negative and positive edge triggered flip-flops available. In theory there shouldn't be timing issues with just have of the period because the clock is not too fast, but I want to avoid this last.

Solution

Since both kinds of flip flops work on the same clock, even on the different edges, they are synchronized.

You need to keep an eye on setup and hold times, and therefore the maximum possible clock frequency.

Your tool chain should be able to check the timing, and to calculate the maximum clock frequency, considering supply voltage and temperature.

Only if you get near the maximum frequency, start thinking about a solution. In any development process, premature optimization is a bad idea.