Iterating over struct members, SystemVerilog

Question

I have a type parameter t, that expects a struct, I then want to; in a generate block, iterate over each named field/member in said struct to generate some code:

typedef struct packed {
   bit       a,
   bit[7:0]  b,
   bit[15:0] c
};

module x #(
  parameter type t = my_struct;
)

generate
  // where here "my_struct[m]" is an individual struct field, not each bit individually.
  foreach(my_struct[m]) begin
    //...
  end
endgenerate

Is there anyway to this?

Answer 1

Structs are objects for individual field selection. Arrays are objects for iteration.

There is no way to do this within the SystemVerilog language. There are ways to iterate over fields of a struct using the Verilog Programming interface (VPI) in C code, but that certainly would not be synthesizable.

You could use the let construct or a `define macro to make it easy to create repetitive code.