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verilogsystem-veriloghdl

Can we disable Always block using disable statement?


module xyz;
  
  always
  begin : b1
    $display("I am executing"); // statement 1
    disable b1;
    $display("I am still executing"); // statement 2    
  end  
  
endmodule  

I am unable to understand how disable statement actually behaves in the above code.

I was expecting that the statement 1 will execute only once and then the always block (b1) will be disabled forever. But actually statement 1 is being executed infinitely (until the process is killed) and statement 2 is being skipped.

I am executing
I am executing
I am executing
      .
      .
      .

I have tried all simulators of EDA Playground.


Solution

  • A disable name statement is essentially a jump to the end of the named block. It does not terminate any processes (except nested fork/join blocks)

    The always construct creates a permanent process that executes the procedural statement that follows it. Once that statement completes, it executes it over again indefinitely. In your example, that procedural statement is a begin/end block