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hdlnand2tetris

Trying to build a PC (counter) for the nand2tetris , but I'm having some trouble with the logic


The project aims to build a program counter.

The description are as follows:

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/PC.hdl

/**
 * A 16-bit counter with load and reset control bits.
 * if      (reset[t] == 1) out[t+1] = 0
 * else if (load[t] == 1)  out[t+1] = in[t]
 * else if (inc[t] == 1)   out[t+1] = out[t] + 1  (integer addition)
 * else                    out[t+1] = out[t]
 */

I figured out all the possibilities as follows All possible output Then here I go:

    CHIP PC 
{
    IN in[16],load,inc,reset;
    OUT out[16];

    PARTS:
    // Put your code here:
    Register(in=in, load=true, out=thein);
    Register(in=in, load=false, out=theout);
    Inc16(in=theout, out=forinc);
    Register(in=forinc, load=true, out=theinc);
    Mux8Way16(a=theout, b=false, c=theinc, d=false, e=thein, f=false, g=thein, h=false, sel[2]=load, sel[1]=inc, sel[0]=reset, out=out);
}

I tried many times but all failed when the clock load to time 1+ or something like this.

Since the register defined here is out(t+1) = out(t)

what is the output of time ?+.I found it really annoying.

Any suggestions will be appreciated.


Solution

  • Some observations:

    1. You're storing the output in a register, which is good. However, note that the register output is also one of your inputs -- it is out[t].

    2. You don't need a big Mux8Way16. There are 4 possible different outputs, so you can either use multiple Mux16s in a cascade or (extra credit) a single Mux4Way16 with some extra logic to compute the two selection bits.

    3. I usually found that the simplest way to do things was first compute all the possible outputs (in this case, 0, input, register+1 or register) and then have the logic to decide which one of those actually gets output.

    Good luck. You are very close.