I am learning Verilog and trying to build a a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.
This is my code:
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
always @(posedge clk) begin
if (reset)
q <= 32'h1;
else begin
integer i;
for (i=0; i<32; i=i+1) begin
case (i)
0 : q[i] <= q[0] ^ q[i+1];
1 : q[i] <= q[0] ^ q[i+1];
21 : q[i] <= q[0] ^ q[i+1];
31 : q[i] <= q[0];
default : q[i] <= q[i+1];
endcase
end
end
end
endmodule
I am facing the following error:
Error (10232): Verilog HDL error at top_module.v(17): index 32 cannot fall outside the declared range [31:0] for vector "q" File: /home/h/work/hdlbits.14205831/top_module.v Line: 17
Most likely because, it is triggering the default condition of the case statement when i=31, but it is not supposed to, as I have already created a separate condition for that.
Can someone please tell me what I am doing wrong?
I am pasting the HDLBits webpage link: https://hdlbits.01xz.net/wiki/Lfsr32
The Verilog code is fine; your case statement compiles cleanly with other simulators.
There is a bug in the tool used by the HDLBits website:
Info: *******************************************************************
Info: Running Quartus Prime Shell
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
You can try to report this as a bug on the Contact page. They might be able to upgrade to a newer version of Quartus released after 2020.
You need to find another way to write your code to run it on that site. Or, you can use another simulator, such as the ones on EDA Playground.
Here is one painful way to get around that bug. Change:
default : q[i] <= q[i+1];
to:
2,3,4,5,6,7,8,9,
10,11,12,13,14,15,16,17,18,19,
20,22,23,24,25,26,27,28,29,30 : q[i] <= q[i+1];
I also tried using the case/inside syntax, but the Quartus tool doesn't support that either.