UVM sequence body task gives unknown compilation error

Question

I have the following code block where a syntax error is fired:

 virtual task body();
     forever begin
    my_transaction m_req;
    // Blocking wait for a transaction request:
    p_sequencer.m_request_fifo.get(m_req);
    // Generate response based on "req_kind" value:
    if ( m_req.req_kind == REQ ) begin
       `uvm_do_with(req, {req_kind == REQ;} )
    end
    else begin
       `uvm_do_with(req, {req_kind == NO_REQ;} )       
    end
     end
  endtask

I get the following error message:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "./src/my_transaction.sv", 77: token is ')'
    if ( m_req.req_kind == REQ ) begin
                                      ^

If I comment the if and else lines as follows, this code block compiles normally:

  virtual task body();
     forever begin
    my_transaction m_req;
    // Blocking wait for a transaction request:
    p_sequencer.m_request_fifo.get(m_req);
    // Generate response based on "req_kind" value:
    //if ( m_req.req_kind == REQ ) begin
       `uvm_do_with(req, {req_kind == REQ;} )
    //end
    //else begin
       `uvm_do_with(req, {req_kind == NO_REQ;} )       
    //end
     end
  endtask

I tried commenting this line:

my_transaction m_req;

as well and expected an error to fire up due to undefined m_req identifier. But the code actually compiles!

The definition of req_kind is:

class my_transaction extends uvm_sequence_item;
   typedef enum {REQ, NO_REQ} req_kind_e;
   rand req_kind_e req_kind;
...
...
...

and the class my_transaction is type forwarded in the file where the compilation error is present:

typedef class my_transaction ;

The code block in question is a sequence in a sequence library where m_request_fifo is the port used in the slave sequencer to retrieve the sequence.

I'm compiling this file along with other files. Is the compiler error message misleading? What other places in code i can look for to know the source of the problem?

What can possibly be the issue?

Answer 1

The source code for the declaration of the uvm_sequence class is:

virtual class uvm_sequence #(
    type    REQ  =  uvm_sequence_item,
    type    RSP  =  REQ
) extends uvm_sequence_base

REQ is a type parameter. Your using it for something else is wrong/confusing your compiler.