Functional Coverage for Verilog based TB

Question

I am currently developing a Verilog based Testbench model for a DUT, I have experience with System Verilog TB and Verification IPs and this is my first time developing a pure verilog TB.

I have completed the basic blocks for running the simulation and its working as expected. But I am stuck at implementing the Functional Coverage(which I want to do in Sample Monitor block).I have extracted the Functional Coverage from the specifications but how do I implement it in Verilog code ?

We have below(example code to show the syntax) support in System verilog for functional coverage,

covergroup example_group @ (posedge en);
  parity : coverpoint  par {
    bins even  = {0};
    bins odd   = {1};
  }
endgroup

Is there a way to implement functional coverage as bins,points and groups(in System verilog) to track overall functional coverage in verilog based code?

Edit : I understood that there is no alternative syntax for coverage in verilog and I don't want to complicate and spend more time by implementing coverage counters. Also I can't convert my verilog TB to System Verilog due to some internal agreement issues.

Answer 1

Yes, the covergroup is equivalent to this Verilog code

always @(posedge en) begin : example_group
                       integer even=0;
                       integer odd=0;
                       if (par == 0) even = even + 1;
                       if (par == 1) odd = odd + 1;
                     end

But the real time consuming part is writing the code that collects all these counters, merges the data from different tests, and generates the reports. Seems silly to re-invent this. Most tools give you this capability in SystemVerilog.