What happens if I dont specify the size and base format for unknown state?

Question

What happens if I do something like

Signal1 = 'x;

as opposed to something like

Signal1 = 4'bxxxx;

Are there any differences? Note that I have previously declared Signal1 as

reg[3:0] Signal1;

Answer 1

This difference is if/when you change the width of Signal1 to be more than 4 bits and forget to change 4'bxxxx, you are going to silently get 0 padding. 'x, 'z, '0, and '0 are all fill literals that expand to width of whatever context they are in.

This is only applicable to SystemVerilog, not Verilog.