I am using Tasks for the first time in Verilog in an attempt to achieve code reuse. I have two tasks, led_on and led_off. I can light up an LED or turn it off with these tasks individually. The problem is when I attempt to run led_blink, a task which combines led_on and led_off tasks, the output led remains undefined until the blink task finishes, leaving the led state matching the last call within the function (led_off, in my example below).
Here's my led_on and led_blink tasks, as well as my task call:
// LED On
task led_on;
inout led;
begin
#10000
led = 1;
end
endtask
// LED Blink
task led_blink;
inout led;
begin
led_on (led);
led_off (led);
led_on (led);
led_off (led);
end
endtask
// Task Call(s)
initial begin
led_blink (led_out);
end
I suspect you are running into trouble with the inout
ports. I have simplified your code by using a reg
named led
which can be set and cleared in your tasks:
module tb;
reg led;
task led_on;
#10000 led = 1;
endtask
task led_off;
#10000 led = 0;
endtask
task led_blink;
begin
led_on ;
led_off;
led_on ;
led_off;
end
endtask
initial begin
$monitor($time, " ", led);
led_blink;
end
endmodule
Outputs:
0 x
10000 1
20000 0
30000 1
40000 0