Verilog Design Problems

Question

How to fix multiple driver , default value and combinational loop problems in the code below?

always @(posedge clk)
  myregister <= #1 myregisterNxt;

always @* begin
  if(reset)
    myregisterNxt = myregisterNxt +1;
  else if(flag == 1)
    myregister = myregister +2;
end

Answer 1

right there are at least 3 issues in your code:

1. you are driving myregister within 2 different always blocks. Synthesis will find multiple drivers there. Simulation results will be unpredictable. The rule: you must drive a signal within a single always block.

2. you ave a zero-delay loop over myregisterNxt = myregisterNxt +1. Since you are using a no-flop there, it is a real loop in simulation and in hardware. You need to break such loops with flops

3. #1 delay is not synthesizable and it is not needed here at all.

You have not described what you were trying to build and it is difficult to figure it out from our code sample. In general, reset is used to set up initial values. So, something like the following could be a template for you.

always @(posedge clk) begin
    if (reset)
       myregister <= 0;
    else 
       myregister <= myregister + increment;
end

always @*  begin
   if (flag == 1) 
      increment = 1;
   else 
      increment = 2;
end

the flop with posedge clk and nonblocking assignments will not be in a loop.