Can a function in verilog call another function?

Question

Consider this following verilog example, is this allowed and is it synthesizable?

function [7:0] func1;
   input [7:0] a;
   input [7:0] b;
   begin
      func1 = func2(a) + b;
   end
endfunction

function [7:0] func2;
   input [7:0] a;
   begin
      func2 = a + a;
   end
endfunction

Answer 1

Yes and yes.

A function is just a way of adding hierarchy to an expression. So, your example is just another way of writing

some_variable = a + a + b;

which is synthesisable, so so are your functions.