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Using enum in verilog

I'm writting a piece of code in Quartus verilog (.v) and I'm trying to write a enum type inside my module:

module Controller(clk, IorD);

    enum {READ, DECODE} state;
    myState = READ;
    //...

But it gives me the following error: Error (10170): Verilog HDL syntax error at Controller.v(3) near text "{"; expecting ";".

What am I doing wrong? How can I use a enum in verilog?

Solution

  • enum is a SystemVerilog feature. You will need to make sure that the file type in Quartus is SystemVerilog (usually the .sv extension is used too)