I have the following comparison statement in verilog, which works fine (positive comparison)
if((count_cc >= 13'b0000000011110)&&(count_cc <= 13'b0000000111100)) //30,60
begin
level=4'b0010; //level 2
end
However, when I use 2's complement, it does not work,
if((count_cc >= 13'b1111111100100)&&(count_cc <= 13'b1111111110110)) //-10 , -28
begin
level=4'b0101; //level 5
end
Any guidance would be helpful.
Assuming count_cc
is already declared signed, use
if((count_cc >= 13'sb1111111100100)&&(count_cc <= 13'sb1111111110110)) //-10 , -28
begin
level=4'b0101; //level 5
end
of course, this would also work
if((count_cc >= -10)&&(count_cc <= -28)