Does a Verilog event control block execution of a procedure?

Question

Does a Verilog event control block execution of a procedure till the event happens? Consider the example below.

module test;
  reg a;
  initial begin
    @(a) $display("%b", a);
    $display("the_message");
  end
endmodule

If I run the above, the simulation ends without the_message printed. Why?

Does this mean that @(a) blocks till a changes? If so, why doesn't the simulation hang forever instead of terminating without printing the_message?

Thanks

Answer 1

Event driven simulators run until there are no more active events scheduled, or explicitly terminated ($finish).