I want to create a 2 dimensional array of constant values as synthesizable Verilog code.
This is for a module that provides the values of a sine wave to a DAC.
reg [7:0] sine [0:19];
initial begin
sine[0] = 8'd0;
sine[1] = 8'd6;
sine[2] = 8'd24;
sine[3] = 8'd53;
sine[4] = 8'd88;
sine[5] = 8'd127;
sine[6] = 8'd167;
sine[7] = 8'd202;
sine[8] = 8'd231;
sine[9] = 8'd249;
sine[10] = 8'd255;
sine[11] = 8'd249;
sine[12] = 8'd231;
sine[13] = 8'd202;
sine[14] = 8'd167;
sine[15] = 8'd127;
sine[16] = 8'd88;
sine[17] = 8'd53;
sine[18] = 8'd24;
sine[19] = 8'd6;
end
When I compile the code there are no errors, but this critical warning occurs:
Critical Warning (127005): Memory depth (32) in the design file differs from memory depth (20) in the Memory Initialization File "__.hdl.mif" -- setting initial value for remaining addresses to 0
Memory Initialization File:
-- begin_signature
-- DAC_SINE
-- end_signature
WIDTH=8;
DEPTH=20;
ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;
CONTENT BEGIN
19 : 00000110;
18 : 00011000;
17 : 00110101;
16 : 01011000;
15 : 01111111;
14 : 10100111;
13 : 11001010;
12 : 11100111;
11 : 11111001;
10 : 11111111;
9 : 11111001;
8 : 11100111;
7 : 11001010;
6 : 10100111;
5 : 01111111;
4 : 01011000;
3 : 00110101;
2 : 00011000;
1 : 00000110;
0 : 00000000;
END;
How can I avoid this critical warning? Do I have to use the minimum memory depth?
I replaced the Verilog module with a System Verilog which now stores the values as 2D array bit parameter (The values don't change). With this modification the critical warning doesn't appear while compilation.
parameter bit [7:0] sine [0:19] = '{8'd0, 8'd6, 8'd24, 8'd53, 8'd88, 8'd127, 8'd167, 8'd202, 8'd231, 8'd249, 8'd255, 8'd249, 8'd231, 8'd202, 8'd167, 8'd128, 8'd88, 8'd53, 8'd24, 8'd6};