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verilogcompiler-optimizationsystem-veriloghdl

Can a sequential always block be triggered by a short pulse from a combi block


Could a sequential always block be triggered by a short lived pulse coming from a combi block ?

I have tried to trigger the always block, by assigning a value and set the value back to 0 in an attempt to trigger the sequential always block but to no avail, below is the pseudo code


always_comb begin
 ...some code...
pulse_trigger = 1;
load_var= driver_var // assigning some values
pulse_trigger = 0;
 ...some code...
end

always @(pulse_trigger)begin
 ...some code part 2...
end

I expect by assigning 1 to pulse_trigger the "always@(pulse_trigger)" block to get activated, but in my VCS simulation this does not seem to be the case.

Maybe this is because the pulse trigger is assigned 1 and unassigned 1 in the same combi block, which takes 0 simulation time, so pulse_trigger might not appear to have changed values. Or this method should've triggered "always@(pulse_trigger)" and executed "...some code part 2..", because I am looking at the wrong values ?


Solution

  • In verilog simulation only a single always block can be evaluated at a time. So, until your always_comb finishes, no other always block can be evaluated. Therefore, no pulse_trigger change will be detected by simulation (because all changes happen inside a single always block.

    You can do something like that by adding delays (assuming this is not a synthesizable code):

    always @* begin
      pulse_trigger = 1;
      load_var= driver_var // assigning some values
      #1 // << this will stop execution of the block for 1 time unit and allow others.
      pulse_trigger = 0;
    end
    

    However, the above code is not synthesizable but it can be a part of a test bench. Also, it is not allowed within always_comb.