Ouput of adder module is always don't care [Verilog]

Question

I know VHDL and now I try to do a bit of verilog. I have two files, one that contains a counter and another that contains a 32 bit full adder.

Counter.v:

module counter (
    input clk,
    input enable,
    input reset,
    output reg [3:0] count
    );


    wire [31:0] temp2 = 0;
    reg [31:0] clk_count = 0;
    wire [31:0] test = 32'b1;

    parameter integer number_of_clk_cycles = 15;
    adder adder1(clk_count, test, temp2);


    always @(posedge clk) begin
        if (reset) begin
            count = 0;
        end else if (enable) begin
            clk_count <= temp2;    
            if(clk_count == number_of_clk_cycles) begin
                count <= count + 1;
                clk_count <= 0;
            end
        end
    end

endmodule

Adder.v:

module adder(
    input [31:0] a,
    input [31:0] b,
    output [31:0] c
    );

    wire [32:0] cin;    //The internal Carry signal
    assign cin[0] = 0;     //Force the carry line to 0, since the first adder has no carry

    genvar i;
    for(i=0; i<32;i = i + 1) begin
        fa fa1( a[i], b[i], cin[i], c[i], cin[i+1]);
    end

endmodule

module ha( a, b, s, c);
    input a, b;
    output s, c;

    xor xor1(s ,a, b);      //Output first, then inputs
    and and1(c, a ,b);        //Output first, then inputs
endmodule

module fa (a , b, cin, s, cout);
    input a, b, cin;
    output s, cout;

    ha ha1(a, b, ha1_sum, ha1_cout);        //Half adder 1
    ha ha2(ha1_sum, cin, s, ha2_cout);        //Half adder 2
    or or1(cout, ha1_cout, ha2_cout);        //Carry out
endmodule

I verified my full adder code in ModelSIM, and it works all the time. But when I try to run the counter.v code, the output adder1 is always 'X' (don't care). If the enable is set to '1' the don't care will ripple through the adder (clk_count <= temp1;). What am I missing?

Answer 1

In verilog, if you drive the same wire with different non-z values, resulting value will be x.

In you case you drive temp2 twice. First time here:

 wire [31:0] temp2 = 0;

which is equivalent to

 wire [31:0] temp2;
 assign temp2 = 0;

and the second time, with the output of your adder.

As a result, if the value produced by the output of the adder is non-zero, temp2 will become x, otherwise it will be 0.

So, do not assign 0 to it.