Variable slicing vector Systemverilog

Question

I am struggling with the error "Range must be constant" when I think it is!

The operation I've to implement is this:

Given a 8 bits signed/unsigned vector and VARIABLE point like : b7b6b5b4b3b2.b1b0 or b7b6b5b4b3.b2b1b0

I have to add the integer part with the first fractional bit, for example:

b7b6b5b4b3b2 + b1 for the first word, b7b6b5b4b3+b2 for the second case.

The number of fractional bits are given by a port named "port_scale" wide C_SHIFT_BITS.

This is my code, I want to generate all the combinations:

C_SHIFT_BITS = 4; 

always_comb begin
   for (int k=1; k<2**(C_SHIFT_BITS-1); k++) begin
       dout_temp[k-1][8:0] = din[(k-1)+:8-k] + din[(k-1)+:1]
   end
   for (int k=1; k<2**(C_SHIFT_BITS-1); k++) begin
       if (port_scale == k) begin
          dout = dout_temp[k][8:0];
       end
   end
end

Do you have another solution or way to code this to make it general? I wouldn't code a massive case statement, since the parameter C_SHIFT_BITS might be any number, less than the width of din. The for loop should workaround the illegal din[port_scale...] but it's not working as expected.

Thanks

Answer 1

I think you simply need to shift by k

 dout_temp[k-1][8:0] = (din >> k-1) + din[k];

Also you can get rid off your second for loop and do

  dout = dout_temp[port_scale][8:0];