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verilogsystem-verilogstate-machineasic

Does enum literal deceleration of states guarantee a glitch free state machine?

does the enum literal deceleration of states for a state machine, guarantee a glitch free behavior as same as one would to assign order as below to the states?

enum { a,b,c} states; 

//vs if you were to declare

parameter a = 3'b000;
parameter b= 3'b010;
parameter c = 3'b011;

/////////////////////////

always @(posedge clk) begin  
  if ( reset) begin
    // initial condition 
    end
  else begin
    case ( state) begin
      a: begin
        state<=b;
      end
      b: begin   
        state<=c;
      end
      c: begin
        state<= a;
      end
      default: state<=c;
    endcase
  end
end
Solution

  • By default, the enum labels get the encodings a=0, b=1, c=2. And you can give explicit encodings:

    enum { a=0,b=2,c=3} states;

    But many synthesis tools have directives to let the tool decide the best encodings for the FSM styles they recognize.