How to ensure a signal is high until another signal has been asserted in System Verilog

Question

I want to check is signal 'a' is high until signal 'b' has been asserted.

signal 'a' should not become 0 before signal 'b' = 1;

How to do it using concurrent assertions?

Answer 1

assert property (@(posedge clk) $rose(A) |-> A throughout B[->1]);